Delivery of high quality parts and controlling production costs are often competing objectives for semiconductor manufacturers as they are for other types of businesses. One area where these objectives compete is in the testing of wafers and integrated circuit packages.
Various test techniques include sequential chain testing or "scan" testing, and built-in self-testing (BIST). Tests that use scan and/or BIST techniques typically require moderate incremental hardware costs. However, the yield rate for circuits subjected to scan and BIST tests alone is not great enough to proceed to package assembly or customer delivery because some circuits may pass the scan and BIST tests and still be inoperable when packaged. Therefore, machine-mode parallel pattern testing and parametric tests are performed after the scan and BIST tests. The drawback to machine-mode and parametric testing is that they require a full complement of channels for signals and power. The result is that duplication of expensive test equipment is required to increase test throughput using conventional parallel test technology with microprocessor and VLSI devices.
A general comparison of tester hardware required for memory devices versus tester hardware required for VLSIs is provided below for the purpose of illustrating the hardware required for machine-mode and parametric testing of VLSIs. VLSI testers do not support the parallel test cost advantages that are inherent in testers for memory devices. This is because VLSI testers effectively require a "complete tester" per signal channel. In other words, VLSI testers are sometimes referred to as "tester-per-pin" or "tester-per-channel" architecture. A memory tester has signal channels that are shared by the internal hardware of the tester for processing test vector information, where a test vector is comprised of addresses and data.
Sharing hardware by multiple signal channels and testing multiple devices in parallel provides a highly efficient parallel test capability for memory testers. However, signal channels of VLSI testers do not share hardware because of the characteristics of VLSI devices. A signal channel of a VLSI tester must support exclusive and unique vector data that is generally random in nature rather than algorithmic. In memory testers, there is generally a simple algorithmic relationship between vector addresses and data to be written to those addresses. Thus vector generation can be accomplished with relatively simple, low-cost hardware, commonly referred to as Algorithmic Pattern Generators (APGs). Because of certain shared characteristics between test vectors, APG units can be shared by signal channels for testing a single memory device, testing multiple memory devices in parallel.
With VLSI testers, the hardware that supports the signal channels must be capable of producing test vectors which are exclusively distinct or different from one signal channel to another signal channel. The widely varying test vectors are not compatible with testers having signal channels shared between hardware. Instead, VLSI testers have exclusively associated with each signal channel a very large storage capability for storing vector information.
A tester which employs for each signal channel, exclusive test vector memory, parametric measurement units, along with standard pin drivers and device output comparators, is referred to as a tester with TESTER-PER-PIN architecture. These types of testers are very expensive given the extensive hardware required.
Conventional parallel testing of microprocessor devices has been found to be expensive relative to the corresponding increase in testing throughput. As explained above, a large part of the expense is driven by the hardware requirements for high-performance machine-mode and parametric testing. In addition, relatively short test times may not justify the hardware expense for parallel testing.